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          Cadence ASM Tutorial
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        <p>最近接触了 Verilog-A。记录一下 Cadence AMS-Designer 数模混合的仿真过程。需要用到的软件有 Cadence IC617, INCISIVE152。</p>
<a id="more"></a>
<blockquote>
<p>INCISIVE152 的安装可以参考 https://blog.csdn.net/yy345730585/article/details/90407408</p>
</blockquote>
<h1 id="初始化设置">初始化设置</h1>
<p>在打开 cadence 的文件夹下面需要新建一个‘<em>hdl.var</em>’文件，内容如下：</p>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line">softinclude <span class="variable">$INCISIVDIR</span>/tools/inca/files/hdl.var</span><br><span class="line">define ams</span><br><span class="line">define NCVLOGOPTS -linedebug</span><br><span class="line">define VIEW_MAP (<span class="variable">$VIEW_MAP</span>, .vs =&gt; shell)</span><br></pre></td></tr></table></figure>
<p>其中 <em>$INCISIVDIR</em> 是 <strong>Cadence INCISIV</strong> 的安装路径。</p>
<p>需要在文件‘<em>cds.lib</em>’中加入一行：</p>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line">SOFTINCLUDE <span class="variable">$INCISIVDIR</span>/tools/inca/files/cds.lib</span><br></pre></td></tr></table></figure>
<h1 id="verilog-a-设计-以理想-dac-为例">Verilog-A 设计 — 以理想 DAC 为例</h1>
<h2 id="ieadl_dac-veriloga-cellview"><em>ieadl_dac (verilogA cellview)</em></h2>
<p><img src="https://pic.zhouyuqian.com/img/20210727174104.png" alt="ieadl_dac" style="zoom:50%;"></p>
<p>首先创建一个新的 Library 叫做 ‘<em>AMS_Tutorial</em>’。然后创建一个 <strong>verilogA</strong> cellview 叫做 ‘<em>ieadl_dac</em>’。文件内容如下：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// VerilogA for AMS_Tutorial, ideal_dac, veriloga</span></span><br><span class="line"></span><br><span class="line"><span class="meta">`<span class="meta-keyword">include</span> &quot;constants.vams&quot;</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">include</span> &quot;disciplines.vams&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> ideal_dac(in, agnd, out);</span><br><span class="line"></span><br><span class="line"><span class="keyword">input</span> [<span class="number">10</span>:<span class="number">0</span>] in;</span><br><span class="line"><span class="keyword">input</span> agnd;</span><br><span class="line"><span class="keyword">output</span> out;</span><br><span class="line">electrical [<span class="number">10</span>:<span class="number">0</span>] in;</span><br><span class="line">electrical agnd;</span><br><span class="line">electrical out;</span><br><span class="line"></span><br><span class="line"><span class="keyword">parameter</span> <span class="keyword">real</span> logic_thresh = <span class="number">2</span><span class="variable">.5</span>;</span><br><span class="line"><span class="keyword">parameter</span> <span class="keyword">real</span> full_scale = <span class="number">1</span><span class="variable">.0</span>;</span><br><span class="line"><span class="keyword">parameter</span> <span class="keyword">real</span> trise = <span class="number">1</span>n from [<span class="number">0</span>:inf);</span><br><span class="line"><span class="keyword">parameter</span> <span class="keyword">real</span> tfall = <span class="number">1</span>n from [<span class="number">0</span>:inf);</span><br><span class="line"></span><br><span class="line"><span class="keyword">real</span> code, delta;</span><br><span class="line"><span class="keyword">real</span> pow2[<span class="number">11</span>:<span class="number">0</span>];</span><br><span class="line"><span class="keyword">integer</span> i;</span><br><span class="line"></span><br><span class="line">analog <span class="keyword">begin</span></span><br><span class="line">    @(initial_step) <span class="keyword">begin</span></span><br><span class="line">        pow2[<span class="number">0</span>] = <span class="number">1</span><span class="variable">.0</span>;</span><br><span class="line">        <span class="keyword">for</span> (i = <span class="number">1</span>; i &lt;= <span class="number">11</span>; i = i+<span class="number">1</span>) <span class="keyword">begin</span></span><br><span class="line">            pow2[i] = <span class="number">2</span><span class="variable">.0</span> * pow2[i-<span class="number">1</span>];</span><br><span class="line">        <span class="keyword">end</span> </span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    code = <span class="number">0</span><span class="variable">.0</span>;</span><br><span class="line">    <span class="keyword">generate</span> j (<span class="number">10</span>,<span class="number">0</span>) <span class="keyword">begin</span></span><br><span class="line">        <span class="keyword">if</span> (V(in[j]) &lt; logic_thresh) <span class="keyword">begin</span></span><br><span class="line">            delta = <span class="number">0</span><span class="variable">.0</span>;</span><br><span class="line">        <span class="keyword">end</span> <span class="keyword">else</span> <span class="keyword">begin</span> </span><br><span class="line">            delta = pow2[j];</span><br><span class="line">        <span class="keyword">end</span></span><br><span class="line">        code = code + delta;</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    <span class="keyword">if</span> (V(in[<span class="number">10</span>]) &gt; logic_thresh) <span class="keyword">begin</span></span><br><span class="line">        code = code - pow2[<span class="number">11</span>];</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    code = full_scale * code / pow2[<span class="number">10</span>];</span><br><span class="line">    V(out) &lt;+ V(agnd) + transition(code, <span class="number">0</span> , trise, tfall);</span><br><span class="line"><span class="keyword">end</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<p>保存后如果没有错误会自动弹出一个创建 symbol 的窗口，确保 symbol 正确创建了。</p>
<h2 id="dac_driver-verilog-cellview"><em>dac_driver (verilog cellview)</em></h2>
<p><img src="https://pic.zhouyuqian.com/img/20210727174132.png" alt="dac_driver" style="zoom:50%;"></p>
<p>然后创建一个 <strong>verilog</strong> cellview 叫做 ‘<em>dac_driver</em>’。文件内容如下：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//Verilog HDL for &quot;AMS_Tutorial&quot;, &quot;dac_driver&quot; &quot;functional&quot;</span></span><br><span class="line"></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> dac_driver (word_out);</span><br><span class="line"></span><br><span class="line">    <span class="keyword">output</span> [<span class="number">10</span>:<span class="number">0</span>] word_out;</span><br><span class="line">    <span class="keyword">reg</span> [<span class="number">10</span>:<span class="number">0</span>] word_out;</span><br><span class="line"></span><br><span class="line">    <span class="keyword">initial</span> <span class="keyword">begin</span></span><br><span class="line">        word_out = <span class="number">12&#x27;h000</span>;</span><br><span class="line">        #<span class="number">20480</span> <span class="built_in">$finish</span>;</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    <span class="keyword">always</span> #<span class="number">5</span> word_out = word_out + <span class="number">1&#x27;b1</span>;</span><br><span class="line"></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<p>保存后如果没有错误会自动弹出一个创建 symbol 的窗口，确保 symbol 正确创建了。</p>
<h2 id="interconnect-elements">interconnect elements</h2>
<p>由于 <em>dac_driver</em> 是一个 Verilog 的 cellview，其输出是数字量，而 <em>ieadl_dac</em> 是一个 verilogA 的 cellview，其输入是模拟量，因此需要 interconnect elements 来进行数字量和模拟量之间的转换。AMS-Designer 可以自动创建 interconnect elements，不过自己来实现这个连接器，连接器应该有两种形式，分别是数字量到模拟量的转换和模拟量到数字量的转换。</p>
<h3 id="a_d-verilogams-cellview"><em>a_d (VerilogAMS cellview)</em></h3>
<p><img src="https://pic.zhouyuqian.com/img/20210727174149.png" alt="a_d" style="zoom:50%;"></p>
<p>创建一个 <strong>VerilogAMS</strong> cellview 叫做 ‘a_d’。文件内容如下：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//Verilog-AMS HDL for &quot;AMS_Tutorial&quot;, &quot;a_d&quot; &quot;verilogams&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="meta">`<span class="meta-keyword">timescale</span> 1ns / 1ps</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">include</span> &quot;constants.vams&quot;</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">include</span> &quot;disciplines.vams&quot;</span></span><br><span class="line"></span><br><span class="line">connectmodule a_d (A, D);</span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> vh = <span class="number">4</span>; <span class="comment">// minimum voltage of a logic 1 (V) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> vl = <span class="number">1</span>; <span class="comment">// maximum voltage of a logic 0 (V) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> c = <span class="number">20</span>f; <span class="comment">// input capacitance (F) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> dt = <span class="number">1</span>m; <span class="comment">// time in x region before x is produced (s) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> dv = <span class="number">0</span><span class="variable">.5</span>; <span class="comment">// voltage between threshold and x region (V)</span></span><br><span class="line">    <span class="keyword">input</span> A; </span><br><span class="line">    <span class="keyword">output</span> D; </span><br><span class="line">    electrical A; </span><br><span class="line">    <span class="keyword">reg</span> D; </span><br><span class="line">    <span class="keyword">logic</span> D; </span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> vlx = vl + dv; </span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> vhx = vh - dv; </span><br><span class="line">    <span class="keyword">reg</span> inXregion;</span><br><span class="line"></span><br><span class="line">    <span class="keyword">always</span> @(above(V(A) - vh)) <span class="keyword">begin</span></span><br><span class="line">        D = <span class="number">1&#x27;b0</span>;</span><br><span class="line">        inXregion = <span class="number">0</span>;</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    <span class="keyword">always</span> @(above(vl - V(A))) <span class="keyword">begin</span></span><br><span class="line">        D = <span class="number">1&#x27;b0</span>;</span><br><span class="line">        inXregion = <span class="number">0</span>;</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    <span class="keyword">always</span> @(above(vhx - V(A))) inXregion = <span class="number">1</span>; </span><br><span class="line">    <span class="keyword">always</span> @(above(V(A) - vlx)) inXregion = <span class="number">1</span>;</span><br><span class="line"></span><br><span class="line">    <span class="keyword">always</span> @(<span class="keyword">posedge</span> inXregion) <span class="keyword">begin</span> : XRegionDelay </span><br><span class="line">        <span class="variable">#(dt/1.0n)</span> <span class="comment">// calculate how many time units are equal to the dt time</span></span><br><span class="line">        D = <span class="number">1&#x27;bx</span>;</span><br><span class="line">        inXregion = <span class="number">0</span>;</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    <span class="keyword">always</span> @(<span class="keyword">negedge</span> inXregion) <span class="keyword">disable</span> XRegionDelay;</span><br><span class="line"></span><br><span class="line">    analog I(A) &lt;+ c*ddt(V(A));</span><br><span class="line"></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<p>保存后如果没有错误会自动弹出一个创建 symbol 的窗口，确保 symbol 正确创建了。</p>
<h3 id="d_a-verilogams-cellview"><em>d_a (VerilogAMS cellview)</em></h3>
<p><img src="https://pic.zhouyuqian.com/img/20210727174202.png" alt="d_a" style="zoom:50%;"></p>
<p>创建一个 <strong>VerilogAMS</strong> cellview 叫做 ‘d_a’。文件内容如下：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//Verilog-AMS HDL for &quot;AMS_Tutorial&quot;, &quot;d_a&quot; &quot;verilogams&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="meta">`<span class="meta-keyword">timescale</span> 1ns / 1ps</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">include</span> &quot;constants.vams&quot;</span></span><br><span class="line"><span class="meta">`<span class="meta-keyword">include</span> &quot;disciplines.vams&quot;</span></span><br><span class="line"></span><br><span class="line">connectmodule d_a (D, A);</span><br><span class="line"></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> v0 = <span class="number">0</span><span class="variable">.0</span>;                <span class="comment">// output voltage for a logic 0 (V) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> v1 = <span class="number">5</span><span class="variable">.0</span>;                <span class="comment">// output voltage for a logic 1 (V) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> vx = <span class="number">2</span><span class="variable">.5</span>;               <span class="comment">// output voltage for a logic x (V) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> vz = <span class="number">5</span><span class="variable">.0</span>;                <span class="comment">// output voltage for a logic z (V) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> r0 = <span class="number">1</span>k from (<span class="number">0</span>:inf);    <span class="comment">// output resistance for a logic 0 (Ohms) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> r1 = <span class="number">1</span>k from (<span class="number">0</span>:inf);    <span class="comment">// output resistance for a logic 1 (Ohms) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> rx = <span class="number">100</span> from (<span class="number">0</span>:inf);   <span class="comment">// output resistance for a logic x (Ohms) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> rz = <span class="number">1</span>M from (<span class="number">0</span>:inf);    <span class="comment">// output resistance for a logic z (Ohms) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> tr=<span class="number">1</span>n from [<span class="number">0</span>:inf);      <span class="comment">// rise time (s) </span></span><br><span class="line">    <span class="keyword">parameter</span> <span class="keyword">real</span> tf=<span class="number">1</span>n from [<span class="number">0</span>:inf);      <span class="comment">// fall time (s)</span></span><br><span class="line"></span><br><span class="line">    <span class="keyword">input</span> D; </span><br><span class="line">    <span class="keyword">output</span> A; </span><br><span class="line">    <span class="keyword">logic</span> D; </span><br><span class="line">    electrical A; </span><br><span class="line">    <span class="keyword">real</span> v, r;</span><br><span class="line"></span><br><span class="line">    <span class="keyword">assign</span> D = D;</span><br><span class="line"></span><br><span class="line">    <span class="keyword">initial</span> <span class="keyword">begin</span></span><br><span class="line">        <span class="keyword">case</span> (D)</span><br><span class="line">            <span class="number">1&#x27;b0</span>: <span class="keyword">begin</span> v = v0; r = r0; <span class="keyword">end</span></span><br><span class="line">            <span class="number">1&#x27;b1</span>: <span class="keyword">begin</span> v = v1; r = r1; <span class="keyword">end</span></span><br><span class="line">            <span class="number">1&#x27;bx</span>: <span class="keyword">begin</span> v = vx; r = rx; <span class="keyword">end</span></span><br><span class="line">            <span class="number">1&#x27;bz</span>: <span class="keyword">begin</span> v = vz; r = rz; <span class="keyword">end</span></span><br><span class="line">        <span class="keyword">endcase</span> </span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    <span class="keyword">always</span> @(D) <span class="keyword">begin</span></span><br><span class="line">        <span class="keyword">case</span> (D)</span><br><span class="line">            <span class="number">1&#x27;b0</span>: <span class="keyword">begin</span> v = v0; r = r0; <span class="keyword">end</span></span><br><span class="line">            <span class="number">1&#x27;b1</span>: <span class="keyword">begin</span> v = v1; r = r1; <span class="keyword">end</span></span><br><span class="line">            <span class="number">1&#x27;bx</span>: <span class="keyword">begin</span> v = vx; r = rx; <span class="keyword">end</span></span><br><span class="line">            <span class="number">1&#x27;bz</span>: <span class="keyword">begin</span> v = vz; r = rz; <span class="keyword">end</span></span><br><span class="line">        <span class="keyword">endcase</span> </span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line">    analog <span class="keyword">begin</span></span><br><span class="line">       V(A) &lt;+ transition(v, <span class="number">0</span>, tr, tf) + transition(r, <span class="number">0</span>, tr, tf)*I(A); </span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>
<p>保存后如果没有错误会自动弹出一个创建 symbol 的窗口，确保 symbol 正确创建了。</p>
<h2 id="ideal_dac_test-schematic-cellview"><em>ideal_DAC_test （schematic cellview）</em></h2>
<p><img src="https://pic.zhouyuqian.com/img/20210727174229.png" alt="ideal_DAC_test" style="zoom:50%;"></p>
<p>创建一个 <strong>schematic</strong> cellview 叫做 ‘ideal_DAC_test’。将器件按照下图进行连接。</p>
<figure>
<img src="https://pic.zhouyuqian.com/img/20210727170838.png" alt="schematic"><figcaption aria-hidden="true">schematic</figcaption>
</figure>
<h1 id="仿真">仿真</h1>
<h2 id="config-config-cellview"><em>config (config cellview)</em></h2>
<h3 id="创建">创建</h3>
<p>为 <em>ideal_DAC_test</em> 创建一个 <strong>config cellview</strong>，如下图所示。</p>
<p><img src="https://pic.zhouyuqian.com/img/20210727174248.png" alt="config" style="zoom: 50%;"></p>
<p>创建完成后，配置窗口会自动弹出，如下图所示，首先选择 ‘Use Template…’，在弹出来的窗口中选择 ‘AMS’。剩下的信息按照下图配置。</p>
<p><img src="https://pic.zhouyuqian.com/img/20210727174302.png" alt="AMSconfig" style="zoom:50%;"></p>
<p>创建完成后，把 config(Hierarchy Editor) 和 Schematic 窗口<strong>都关闭</strong>。</p>
<h3 id="配置-view-to-use">配置 <em>View To Use</em></h3>
<p>然后<strong>再次打开 config 窗口</strong>，这时会弹出一个窗口，两项都选 ‘yes’，如下图所示。</p>
<p><img src="https://pic.zhouyuqian.com/img/20210727174315.png" alt="reopen" style="zoom:50%;"></p>
<p>点击 ‘OK’ 之后会看到 config 和 schematic 窗口都一起打开了。在 Hierarchy Editor 窗口中，右击 <em>View To Use</em> 上右击，选择 <em>Select View</em>，配置成如下图所示。</p>
<figure>
<img src="https://pic.zhouyuqian.com/img/20210727170839.png" alt="view"><figcaption aria-hidden="true">view</figcaption>
</figure>
<p><img src="https://pic.zhouyuqian.com/img/20210727174329.png" alt="AMS_view" style="zoom:50%;"></p>
<h3 id="配置-ams">配置 AMS</h3>
<p>点击 Plugins -&gt; AMS，然后 AMS 选项就会出现在 Hierarchy Editor 窗口中了。</p>
<p><img src="https://pic.zhouyuqian.com/img/20210727174347.png" alt="AMS_Plugin" style="zoom: 50%;"></p>
<p>然后点击 AMS -&gt; Initialize，配置 <em>Run Directory</em>，并且在 <em>Always use this run directory …</em> 后面打钩。</p>
<p><img src="https://pic.zhouyuqian.com/img/20210727174357.png" alt="AMS_Initialize" style="zoom:50%;"></p>
<p>在 AMS -&gt; Quick Setup 中，配置 <em>hdl.var</em> 为之前<a href="#初始化设置">初始化设置</a>中创建的 <em>hdl.var</em> 文件。</p>
<p><img src="https://pic.zhouyuqian.com/img/20210727174410.png" alt="AMS_quicksetup" style="zoom:50%;"></p>
<p>在 AMS -&gt; Detalied Setup -&gt; Analyses 中设置仿真结束时间，这里设置的是 <em>20e-6</em>。</p>
<p><img src="https://pic.zhouyuqian.com/img/20210727174424.png" alt="stoptime" style="zoom:50%;"></p>
<p>上面几步做完了记得保存一下。</p>
<h2 id="运行仿真">运行仿真</h2>
<p>点击 AMS -&gt; NetList and Run，打开一个 config 窗口，这里也可以设置仿真时间。需要注意的是 <em>Save/Plot…</em> 这个选项，该选项可以将需要观察的信号添加进来，不过不建议在这里添加，而是 Netlist 之后再添加，更加方便。</p>
<p><img src="https://pic.zhouyuqian.com/img/20210727174435.png" alt="AMS_run_config" style="zoom:50%;"></p>
<p>在上面的窗口中点击 <em>Run</em>，如果没有错误会弹出 SimVision 窗口。</p>
<p>在 <em>Design Browser</em> 窗口中想要观察的信号上右击 -&gt; <strong>Send to Waveform Window</strong>，然后再点击 SimVision Console 窗口中的 <strong>Run</strong> 按钮，仿真就开始运行了。</p>
<figure>
<img src="https://pic.zhouyuqian.com/img/20210727170840.png" alt="SimVision"><figcaption aria-hidden="true">SimVision</figcaption>
</figure>
<figure>
<img src="https://pic.zhouyuqian.com/img/20210727170841.png" alt="wave"><figcaption aria-hidden="true">wave</figcaption>
</figure>
<blockquote>
<p>PS：如果模拟量信号观察不到，但可以看到数值，可能需要设置一下 View -&gt; Zoom -&gt; Full Y.</p>
</blockquote>
<hr>
<h1 id="reference">Reference</h1>
<ul>
<li><p><a target="_blank" rel="noopener" href="https://wenku.baidu.com/view/cbd263c8192e45361166f5e5.html">Tufts University Cadence AMS-Designer Tutorial</a></p></li>
<li><p>https://blog.csdn.net/YYP_8020/article/details/107332430</p></li>
<li><p>Cadence Verilog-AMS Language Reference</p>
<p>$INSTALL_DIR/doc/verilogamsref/verilogamsref.pdf</p></li>
<li><p>Virtuoso AMS Simulator User Guide</p>
<p>$INSTALL_DIR/doc/amssimug/amssimug.pdf</p></li>
<li><p>Cadence NC-Verilog Simulator Tutorial with SimVision</p>
<p>$INSTALL_DIR/doc/ncvlogtut/ncvlogtut.pdf</p></li>
<li><p>https://designers-guide.org/index.html</p></li>
</ul>

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        <div style="text-align:center;color: #ccc;font-size:14px;">-------The end of this article&nbsp;<i class="fa fa-paw"></i>&nbsp;Thank you for your reading-------</div>
    
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    <strong>本文作者： </strong>Fitz
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    <strong>本文链接：</strong>
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